An All Digital Phase-Locked Loop (ADPLL) can be used to generate clocks in digital and analog circuits. In a frequency divider based ADPLL, a reference clock and a divider clock are mutually asynchronous during a phase locking stage and the phase relation between the reference clock and the divider clock is known during a phase tracking stage when phase lock is achieved. In a frequency divider based ADPLL, clock synchronization between a reference clock and a divider clock may introduce metastability and/or increase noise. For example, a one-flop synchronizer may enter metastability during a phase tracking stage because the reference clock can change simultaneously with a sampling edge of the divider clock.